By G.E. Taylor, G. Russell
This ebook covers algorithms and functions of strategies from the bogus intelligence group in CAD for VLSI.
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Additional info for Algorithmic and knowledge based CAD for VLSI
Proceedings 26th ACM/IEEE Design Auto. Conference, 1989. , "Formal System Design - Interactive Synthesis Based on Computer-Assisted Formal Reasoning", Proceedings IFIP Workshop - Applied Methods for Correct VLSI Design, Belgium, 1989. GORDON M. "HOL, A Proof Generating System for Higher Order Logic" - VLSI Specification, Verification and Synthesis", G. Birtwhistle and P. A. Subramanyam (Eds), Kluwer, 1987. , "FM8501: A Verified Microprocessor", PhD Thesis, University of Texas at Austin, 1985. IEEE Standard VHDL Language Reference Manual, IEEE Press, 1987.
When the transformations and hardware allocation have been completed, a STRICT description of the complete design is generated, and the final layout can then be generated using standard floorplanning and routing tools. The interactive interface of the synthesis tool is shown in Figure 2. The functional tree for one level in the design hierarchy is displayed in the centre of the screen. Below it is its lisp description. Interaction with the functional tree takes place by clicking on the icons which are situated around the edges of the screen.
To deallocate, the DEALLOC icon is selected followed by a previously allocated node. In this case the node is replaced by the subtree representing the behaviour of the particular hardware module. Allocation of a functional tree can be carried out automatically by clicking on the AUTOALL icon. This causes the tool to search the library of hardware modules and map them directly to the functional tree. The MRG/SPL icon is used for space-time transformations. Finally the EXIT icon is used for exiting from the synthesis tool.
Algorithmic and knowledge based CAD for VLSI by G.E. Taylor, G. Russell