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By Rajeev Alur; T A Henzinger; Stanford University. Computer Science Department

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The resulting module module Pete2 is hide . . in R1 R2 Rx should have the same abstract type and the same traces as the module Pete. (c) How would you change the definition of Rx in part (a) if x is a nonnegativeinteger variable rather than a boolean variable? 30 uses many rounds for a single handshake. The two protocols have identical receiver agents. Every send-receive cycle of AsyncMsg consists of four phases —a message production phase, an agent coordination phase, a message transmission phase, and a message consumption phase— each consisting of any number of update rounds.

If both updated input values are 0, then the state of the latch (which is equal to the already updated output out ) does not change. If both updated input values are 1, then the next state of the latch is arbitrary —it may be either 0 or 1 (in this case, two of the guards apply, and the value of state is updated nondeterministically). What remains to be specified are the initial values of out and state. The initial output of the latch is arbitrary (this is a second source of nondeterminism). The initial state of the latch is computed combinationally from the initial values of out, set, and reset as during update rounds (in particular, if both set and reset are initially 0, then the initial value of state is determined by the initial value of out).

The event variables req R , grant R , and release R refer to the philosopher to the right. (a) Define a passive module Phil which implements a philosopher and, using multiple, renamed copies of Phil and Stick , define a compound module Dine4 which implements the dining-philosophers scenario for n = 4. Illustrate the communication structure of the module Dine4 by drawing block diagrams for Phil , Stick , and Dine4 at suitable levels of abstraction. (b) Give an initialized trajectory of your module Dine4 which ends up in a situation where all 4 philosophers sit at the table, Reactive Modules 56 module Stick is private pc : {free, left, right} interface grant L , grant R : E external req L , release L , req R , release R : E passive atom controls pc, grant L , grant R reads pc, req L , grant L , release L , req R , grant R , release R awaits req L , release L , req R , release R init [] true → pc := free update [] pc = free ∧ req L ?

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A really temporal logic by Rajeev Alur; T A Henzinger; Stanford University. Computer Science Department


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